Scaling of devices has been instrumental in the improvements in speed and power consumption of devices, e.g., transistor technologies in RF applications. Although technology has progressed significantly, such evolution (scaling) of the devices is becoming increasingly more difficult. For example, back end of the line (BEOL) and middle of the line (MOL) metallization is becoming more challenging in advanced technology nodes due to the critical dimension (CD) scaling and process capabilities.
These challenges include the difficulty in controlling etching processes. For example, it has been observed in conventional device fabrication processes that the etching process can result in a punch through effect; that is, an etching process for a gate contact can attack insulator material and expose the source/drain regions or contacts of the source drain contacts (and vice versa). Due to this exposure, the metallization for the gate contact can land on both the gate metal and the source/drain silicide or contact regions.